Today's integrated circuits (ICs) exchange information with each other and with other components at very high data rates. Typically, information is sent from a transmitter on one IC to a receiver on another IC through a series of analog pulses on a communications channel. Specifically, to send a digital bit of information, a transmitter determines whether the bit it wants to send is a digital 1 or a digital 0. If the bit is a digital 1, the transmitter generates an analog signal (which may be made up of a single signal or a pair of differential signals) having a positive voltage. If the bit is a digital 0, the transmitter generates an analog signal having a negative voltage. After generating the analog signal, the transmitter sends the analog signal as a pulse having a certain duration to the receiver along the communications channel. Upon receiving an analog pulse, the receiver determines whether the analog signal has a positive voltage or a negative voltage. If the voltage is positive, the receiver determines that the analog signal represents a digital 1. If the voltage is negative, the receiver determines that the analog signal represents a digital 0. In this manner, the transmitter is able to provide digital information to the receiver using analog signals.
A series of analog signals is transmitted by transmitting a series of analog pulses, each having a certain duration and each having either a positive voltage or negative voltage depending on whether the transmitter is sending a digital 1 or a digital 0 during the duration. The number of analog pulses that are transmitted during a particular period of time depends on the length of the duration of each of the analog pulses. This is also the number of digital bits that are communicated from the transmitter to the receiver during the particular period of time, and is referred to as the data rate. For example, if an analog pulse is transmitted once every billionth of a second, then one billion digital bits can be communicated in a second, and the data rate is 1,000,000,000 bits per second. Today's ICs typically exchange information at data rates of at least 1 gigabit per second.
At such high data rates, jitter in the analog signal received by IC receivers poses a serious problem. A receiver can recover a clock signal from a received analog signal and use the recovered clock signal to sample the analog signal in order to determine whether the analog signal that is received during a duration of time, or clock cycle, is positive or negative. When the analog signal contains jitter, however, the clock signal that is recovered from the analog signal will also contain jitter that is out of phase with the jitter in the analog signal. As a result, using this recovered clock signal introduces timing error into the receiver's sampling of the analog signal and may result in erroneous determinations of whether an analog signal represents a digital 1 or digital 0 during a duration of time. To account for this timing error, the receiver must sample the data signal during a period of time in the clock cycle in which the analog signal is not affected by its jitter. Effectively, this reduces the amount of timing budget that is available to the receiver for sampling the analog signal.
In one solution to the jitter problem, a clock signal is sent from the transmitter to the receiver along with the analog signal. This clock signal is often referred to as a “forwarded clock” and has a clock rate that is substantially the same as half of the data rate of the analog signal. The analog signal is also referred to as the data signal. For example, if the data rate of the data signal is 1 gigabit per second, then the clock rate of the forwarded clock would be 0.5 gigahertz. In another words, one clock cycle, which typically consists of two time periods where the clock signal is positive in the first time period and negative in the second time period, corresponds to two data unit cycles.
In addition, the forwarded clock contains an amount of timing error that is substantially the same as the timing error caused by the jitter in the data signal. This forwarded clock is then used by the receiver to recover data from the data signal. Because the forwarded clock contains a timing error that correlates with the timing error in the data signal, using the forwarded clock to sample the data signal reduces errors in sampling the data signal and results in a larger timing budget for the receiver.
Ideally, the forwarded clock would have a 50% positive duty and a 50% negative duty, like clock signal 100 pictured in FIG. 1. Clock signal 100 has a positive duty 102 that is equal to the negative duty 104. A clock signal that has a 50% positive duty and a 50% negative duty has no duty cycle distortion because the positive duty is equal to the negative duty.
Duty cycle distortion, or DCD, refers to deviations, in a clock signal, from the ideal 50-50 duty cycle. FIG. 2 illustrates a clock signal 200 that has DCD. More specifically, clock signal 200 in FIG. 2 has a positive duty 202 that is less than 50% and a negative duty 204 that is more than 50%. When a clock signal contains DCD, the amount of time between the rising edge of the clock signal and the falling edge of the clock signal (202) does not match the amount of time between the falling edge of the clock signal and the rising edge of the clock signal (204). DCD can be caused by a mismatch in device characteristics between P-type transistors and N-type transistors, which results in asymmetry between a clock signal's rising edge and falling edge. However, since these edges are used by a receiver to sample the data signal, the receiver must sample the data signal during a period of time in the clock cycle in which the clock signal is not affected by DCD. Thus, DCD reduces the amount of timing budget that is available to the receiver.
Furthermore, when a high-frequency clock signal, such as clock signals over 2 gigahertz, is transmitted over a lossy channel, the DCD of the clock signal becomes amplified. A lossy channel in general is a data channel where signal loss cannot be ignored. Unless very specially designed, lossy channels have higher attenuation for high frequency components and lower attenuation for low frequency components. In FIG. 3, dotted waveform 306 represents the clock signal 200 that is depicted in FIG. 2, and clock signal 300 is clock signal 200 after transmission through a lossy channel. As FIG. 3 illustrates, clock signal 300 is attenuated relative to clock signal 200. Furthermore, clock signal 300 is attenuated such that the positive duty 302 is even less than the positive duty 202 in clock signal 200. Also, the negative duty 304 of clock signal 300 is even bigger than the negative duty 204 in clock signal 200. The overall result is that the DCD of clock signal 300 is larger than the DCD of clock signal 200. In other words, the DCD of clock signal 300 is amplified relative to the DCD of clock signal 200. Experimental data indicates that the DCD of a clock signal can be amplified five times or more of the original DCD after being transmitted over a lossy channel. This has the effect of significantly reducing the timing budget available to the receiver.
Since data signals transmitted between today's ICs are transmitted over lossy channels and often have data rates over 2 gigahertz, DCD amplification is a significant problem in IC communications. This problem is especially prominent in lossy channels where the clock signal experiences at least a −6 dB loss at the frequency of the clock rate (for example, when the 500 MHz frequency component of a 500 MHz clock experiences a −6 db loss on the lossy channel). Although reducing the DCD in clock signals that are transmitted is one solution, techniques for doing so involve significant design time and expensive components in the transmitter. Thus, a practical solution for reducing the amplification of DCD of clock signals at high frequencies is needed.